Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks
Published in 2019 International Conference on Field-Programmable Technology, 2019
Today's FPGA compilation is slow because it compiles and co-optimizes the entire design in one monolithic mapping flow. This achieves high quality results but also means a long edit-compile-debug loop that slows development and limits the scope of design-space exploration. We introduce PRflow that uses partial reconfiguration and an overlay packet-switched network to separate the HLS-to-bitstream compilation problem for individual components of the FPGA design.
Recommended citation: Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, and Andre DeHon. Re-ducing FPGA compile time with separate compilation for FPGA building blocks. In 2019 International Conference on Field-Programmable Technology (ICFPT), pages 153–161. IEEE, 2019 http://ic.ese.upenn.edu/pdf/prflow_fpt2019.pdf